Irvine, CA (PressExposure) April 07, 2009 -- Advanced Architectures LLC, a design services and semiconductor intellectual property company, announced today the availability of its A2P processor. A2P contains new levels of micro-architecture flexibility which delivers significant improvements in power consumption and area for SoC subsystems when compared to conventional approaches using embedded or reconfigurable processors.
As the features and complexity of SoCs grow, SoC architectures today are now supporting a host processor and one to several subsystems, which are themselves processors tightly coupled with their own local resources. Subsystems that support differentiable functions, such as video image enhancement or multi-protocol communications processing, face two challenges: - Ensuring support for the differentiating features, usually an algorithm with unique requirements that must be converted into hardware, results in optimal price-performance-power (algorithm-to-hardware translation efficiency). - The integration of the subsystem has the most minimal impact possible on the global SoC architecture (subsystem integration efficiency).
The rigid micro-architectures of embedded or first generation reconfigurable processors typically hinder the translation and integration efficiencies which necessitates trade-offs in performance, power and area. A2P improves the efficient algorithm-to-hardware translation, and eases the subsystem integration when compared to conventional approaches. "We have already demonstrated as much as a 20% area and 40% power reduction when replacing conventional processor based subsystems with A2P functional equivalents." said Roger Thorpe, president Advanced Architectures. "A2P achieves these gains because tuning the micro-architecture enables the resulting instantiation to be far more efficient in terms of its transistor utilization. A2P also reduces global traffic up to 50% because it makes better use of the subsystem's data paths and local memories."
Typical A2P based applications include video streaming and multi-protocol communications. For example, DTV SoCs perform MPEG4 (H.264) decoding, and also support image enhancement features, such as anti-blurring. While the decoding is common to many DTV chips today, image enhancement provides valuable differentiation. Since the algorithms used for image enhancement often have unique requirements, achieving optimal algorithm-to-hardware translation efficiency is difficult using conventional approaches.
But by tuning the A2P micro-architecture, a better match is made between the algorithm's unique needs and the threading required by the processor to support those needs. This minimizes area, power, and also reduces global bus traffic and memory subsystem complexity. And since A2P deliverables include a port of the popular ThreadX operating system, these advantages are directly visible to software developers. "A2P's ability to create and manage threads at the micro-architecture level complements the proven ability of ThreadX such that new levels of software efficiency and control can be achieved." says William E. Lamie, president, Express Logic.
A2P is sold under a licensing structure typical of the EDA industry. Current A2P customers have already achieved successful tape-outs and are in volume production.